FPGA-based high performance page layout segmentation
نویسندگان
چکیده
A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2 { an FPGA based array processor. The synthesis speed as determined by the Xilinx synthesis tools projects the applications speed of 5 MHz. For documents of size 1,024 1,024 pixels, a signiicant speedup in the range of 250 has been achieved.
منابع مشابه
FPGA-based of Thermogram Enhancement Algorithm for Non-destructive Thermal Characterization
متن کامل
Persian Printed Document Analysis and Page Segmentation
This paper presents, a hybrid method, low-resolution and high-resolution, for Persian page segmentation. In the low-resolution page segmentation, a pyramidal image structure is constructed for multiscale analysis and segments document image to a set of regions. By high-resolution page segmentation, by connected components analysis, each region is segmented to homogeneous regions and identifyi...
متن کاملMethodology for Flexible and Efficient Analysis of the Performance of Page Segmentation Algorithms
This paper presents part of a new DIA performance analysis framework aimed at Layout Analysis algorithm developers. A new region-representation scheme (an interval-based description of isothetic polygons) and a corresponding comparison approach are introduced. These enable fast and accurate geometric comparison of ground-truth with results of page segmentation, improving on current evaluation m...
متن کاملHigh Performance Custom Computing for Image Segmentation
The use of dynamic instruction architectures based on eld-programmable gate arrays (FPGAs) is described. Using this approach, an application speciic instruction based system has been designed for image segmentation which is an important stage in a computer vision system. The speciic application of interest here is texture-based page layout segmentation for document images. The complete segmenta...
متن کاملPerformance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA
A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multilevel network with the logic blocks placed at different Tree levels using ButterflyFat-Tree network topology. 2D physical layout development of a Tree-based multilevel interconne...
متن کامل