FPGA-based high performance page layout segmentation

نویسندگان

  • Nalini K. Ratha
  • Anil K. Jain
  • Diane T. Rover
چکیده

A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2 { an FPGA based array processor. The synthesis speed as determined by the Xilinx synthesis tools projects the applications speed of 5 MHz. For documents of size 1,024 1,024 pixels, a signiicant speedup in the range of 250 has been achieved.

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تاریخ انتشار 1996